1. Field of the Invention
The present invention pertains to a method of sputtering a sculptured coating over the walls of a high aspect ratio semiconductor feature in a manner which avoids or significantly reduces the possibility of damage to or contamination of underlying surfaces.
2. Brief Description of the Background Art
As the feature size of semiconductor patterned metal features has become increasingly smaller, it is particularly difficult to use the techniques known in the art to provide multilevel metallurgy processing. In addition, future technological requirements include a switch from the currently preferred metallurgy of aluminum to copper in some applications, because of copper's lower resistivity and higher electromigration resistance. The standard reactive ion etching method frequently used for patterning a blanket metal is particularly difficult with copper, since there are no volatile decomposition products of copper at low temperatures (less than about 200° C.). The alternative deposition lift-off techniques are also limited in applicability in a copper structure, given the susceptibility of copper to corrosion by the lift-off solvents. Therefore, the leading process for formation of copper-comprising devices is a damascene structure, which requires the filling of embedded trenches and/or vias.
A typical process for producing a damascene multilevel structure having feature sizes in the range of 0.5 micron (μ) or less would include: blanket deposition of a dielectric material; patterning of the dielectric material to form openings; application of a barrier layer over the surface of the dielectric material; deposition of a conductive material onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using a chemical, mechanical, or combined technique such as chemical-mechanical polishing. When the feature size is below about 0.25μ, typically the barrier layer and/or the conductive fill layer are deposited using a method selected from chemical vapor deposition (CVD), evaporation, electroplating, or ion deposition sputtering. Chemical vapor deposition, being completely conformal in nature, tends to create voids in the center of the filled opening, particularly in the instance of high aspect ratio features. Further, contaminants from the deposition source are frequently found in the deposited conductive material, which may affect adhesion and other film properties. Evaporation is successful in covering shallow features, but is generally not practical for the filling of high aspect ratio features, in part because the deposition rate for the evaporation technique is particularly slow, and also because of poor step coverage. Electroplating has recently shown promise as a method of filling contact vias, but the crystal orientation of electroplated copper is not optimum for the reduction of electromigration unless a proper seed layer is deposited prior to electroplating. Sputtered copper has been used to provide a seed layer over which a fill layer of electroplated copper or CVD copper can be applied, to improve crystal structure and improve device performance.
No matter which technique is used for the application of copper, prior to that application it is necessary to apply a barrier layer which prevents the diffusion of copper into adjacent materials. The barrier layer needs to be continuous and free from any openings which might permit the diffusion of copper atoms. Formation of such a continuous barrier layer is particularly difficult when the barrier layer must cover the surface of a feature having an aspect ratio of greater than about 3:1 and a feature size of 0.5μm or less. The preferred method of application of a barrier layer is physical vapor deposition (PVD) with plasma sputtering being preferred among the PVD methods, due to the higher deposition rates obtainable using this method. Traditional plasma sputtering is used when possible, due to simplicity of the equipment required to carry out deposition. In some instances, when particularly small feature sizes are involved, less than 0.25μ, for example, it may be necessary to use ion-deposition plasma (IMP) sputtering techniques.
Due to the difficulty in sculpturing a coating layer, whether it be a barrier layer, or a principally conductive layer, to fit a high aspect ratio, small dimensioned feature, a number of techniques have been developed in an attempt to provide the properly-shaped coating layer.
U.S. Pat. No. 5,312,509 of Rudolph Eschbach, issued May 17, 1974, discloses a manufacturing system for low temperature chemical vapor deposition (CVD) of high purity metals. In particular, a semiconductor substrate including etched patterns is plasma cleaned, sputter coated with adhesion and nucleation seed layers, and a conductive layer is then applied using CVD. The CVD deposited metal is formed using a complex combination of reactor and substrate conditions which are controlled using a computer guidance system. This manufacturing system is recommended for the CVD deposition of pure copper at low temperatures.
U.S. Pat. No. 4,514,437 to Prem Nath, issued Apr. 30, 1985, discloses a method and apparatus for depositing thin films, such as indium tin oxide, onto substrates. The deposition comprises one step in the fabrication of electronic, semiconductor and photovoltaic devices. An electron beam is used to vaporize a source of solid material, and electromagnetic energy is used to provide an ionizable plasma from reactant gases. By passing the vaporized solid material through the plasma, it is activated prior to deposition onto a substrate. In this manner, the solid material and the reactant gases are excited to facilitate their interaction prior to the deposition of the newly formed compound onto the substrate.
U.S. Pat. No. 4,944,961 to Lu et al., issued Jul. 31, 1990, describes a process for partially ionized beam deposition of metals or metal alloys on substrates, such as semiconductor wafers. Metal vaporized from a crucible is partially ionized at the crucible exit, and the ionized vapor is drawn to the substrate by an imposed bias. Control of substrate temperature is said to allow non-conformal coverage of stepped surfaces such as trenches or vias. When higher temperatures are used, stepped surfaces are planarized. The examples given are for aluminum deposition, where the non-conformal deposition is carried out with substrate temperatures ranging between about 150° C. and about 200° C., and the planarized deposition is carried out with substrate temperatures ranging between about 250° C. and about 350° C.
U.S. Pat. No. 4,976,839 to Minoru Inoue, issued Dec. 11, 1990 discloses a titanium nitride barrier layer of 500 Å to 2,000 Å in thickness formed by reactive sputtering in a mixed gas including oxygen in a proportion of 1% to 5% by volume relative to the other gases, comprising an inert gas and nitrogen. The temperature of the silicon substrate during deposition of the titanium nitride barrier layer ranged between about 350° C. and about 500° C. during the sputtering, and the resistivity of the titanium nitride film was “less than 100 μΩ-cm”.
U.S. Pat. No. 5,246,885 to Braren et al., issued Sep. 21, 1993, proposes the use of a laser ablation system for the filling of high aspect ratio features. Alloys, graded layers, and pure metals are deposited by ablating targets comprising more than one material using a beam of energy to strike the target at a particular angle. The ablated material is said to create a plasma composed primarily of ions of the ablated material, where the plasma is translated with high directionality toward a surface on which the material is to be deposited. The preferred source of the beam of energy is a UV laser. The heating of the deposition surface is limited to the total energy deposited by the beam, which is said to be minimal.
S. M. Rossnagel and J. Hopwood describe a technique of combining conventional magnetron sputtering with a high density, inductively coupled RF plasma in the region between the sputtering cathode and the substrate in their 1993 article titled “Metal ion deposition from ionized magnetron sputtering discharge”, published in the J. Vac. Sci. Technol. B. Vol. 12, No. 1, January/February 1994. One of the examples given is for titanium nitride film deposition using reactive sputtering, where a titanium cathode is used in combination with a plasma formed from a combination of argon and nitrogen gases. The resistivity of the films produced ranged from about 200 μΩ-cm to about 75μΩ-cm, where higher ion energies were required to produce the lower resistivity films. The higher the ion energy, the more highly stressed the films, however. Peeling of the film was common at thicknesses over 700 Å, with depositions on circuit topography features delaminating upon cleaving.
S. M. Rossnagel and J. Hopwood describe a technique which enables control of the degree of directionality in the deposition of diffusion barriers in their paper titled “Thin, high atomic weight refractory film deposition for diffusion barrier, adhesion layer, and seed layer applications” J. Vac. Sci. Technol. B 14(3), May/June 1996. In particular, the paper describes a method of depositing tantalum (Ta) which permits the deposition of the tantalum atoms on steep sidewalls of interconnect vias and trenches. The method uses conventional, non-collimated magnetron sputtering at low pressures, with improved directionality of the depositing atoms. The improved directionality is achieved by increasing the distance between the cathode and the workpiece surface (the throw) and by reducing the argon pressure during sputtering. For a film deposited with commercial cathodes (Applied Materials Endura® class; circular planar cathode with a diameter of 30 cm) and rotating magnet defined erosion paths, a throw distance of 25 cm is said to be approximately equal to an interposed collimator of aspect ratio near 1.0. In the present disclosure, use of this “long throw” technique with traditional, non-collimated magnetron sputtering at low pressures is referred to as “Gamma sputtering”. Gamma sputtering enables the deposition of thin, conformal coatings on sidewalls of a trench having an aspect ratio of 2.8:1 for 0.5μm-wide trench features. However, Gamma sputtered TaN films exhibit a relatively high film residual compressive stress which can cause a Ta film or a tantalum nitride (e.g. Ta2N or TaN) film to peel off from the underlying substrate (typically silicon oxide dielectric). In the alternative, if the film does not peel off, the film stress can cause feature distortion on the substrate (typically a silicon wafer) surface or even deformation of a thin wafer.
U.S. Pat. No. 5,354,712 to Ho et al., issued Oct. 11, 1994, describes a method for forming interconnect structures for integrated circuits. Preferably, a barrier layer of a conductive material such as sputtered titanium nitride (TiN) is deposited over a trench surface which is defined by a dielectric layer. The TiN provides a seed layer for subsequent metal deposition. A conformal layer of copper is selectively deposited over the conductive barrier layer using CVD techniques.
U.S. Pat. No. 5,585,763, issued to Joshi et al. on Dec. 17, 1996, discloses refractory metal capped low resistivity metal conductor lines and vias. In particular, the low resistivity metal is deposited using physical vapor deposition (e.g., evaporation or collimated sputtering), followed by chemical vapor deposition (CVD) of a refractory metal cap. Recommended interconnect metals include AlxCuy (wherein the sum of x and y is equal to one and both x and y are greater than or equal to zero). The equipment required for collimated sputtering is generally difficult to maintain and difficult to control, since there is a constant build up of sputtered material on the collimator over time. Collimated sputtering is described in U.S. Pat. No. 5,478,455 to Actor et al., issued Dec. 26, 1995. Collimation, whether for sputtering or evaporation, is inherently a slow deposition process, due to the reduction in sputtered flux reaching the substrate.
U.S. Pat. No. 6,605,197, of the present applicants, issued Aug. 12, 2003, describes a method of filling features on a semiconductor workpiece surface with copper using sputtering techniques. The surface temperature of the substrate is controlled within particular temperature ranges during application of the copper layer. The sputtering method is selected from a number of potential sputtering methods, including gamma sputtering, coherent sputtering, IMP (ion metal plasma), and traditional sputtering, all of which are described in detail. The content of U.S. Pat. No. 6,605,197 is hereby incorporated by reference in its entirety.
U.S. Pat. No. 5,962,923 of Xu et al., issued Oct. 5, 1999, assigned to the Assignee of the present invention, and hereby incorporated by reference in its entirety, describes a method of forming a titanium nitride-comprising barrier layer which acts as a carrier layer. The carrier layer enables the filling of apertures such as vias, holes or trenches of high aspect ratio and the planarization of a conductive film deposited over the carrier layer at reduced temperatures compared to prior art methods. The Xu et al. preferred embodiment carrier layer is a Ti/TiN/Ti three layered structure which is deposited using ion deposition (or ion metal plasma) sputtering techniques. FIG. 1 of the present application shows a schematic of a cross-sectional view of a contact via which includes the carrier layer of Xu et al. In particular, FIG. 1 shows an exemplary contact 118 formed in a high aspect ratio aperture 113. Specifically, aperture 113 has an aspect ratio of about 5:1, where dimension 120 is about 0.25μ wide and dimension 122 is about 1.2μ. The contact 118 includes at least two sub-elements. A carrier layer 100, which also acts as a barrier layer, and a conductive material 119 which has been deposited over the carrier layer 100, to fill the volume of the aperture remaining after the carrier layer has been deposited.
With reference to carrier/barrier layer 100, this three-layered structure is formed from a first sub-layer 112 of titanium which was sputtered from a target and partially ionized (10% to 100% ionization) prior to being deposited on the surface of both silicon dioxide layer 111 and silicon base 110. The technique wherein the target material is ionized after leaving the target and prior to deposition on the substrate is referred to as “ion deposition sputtering” or as “ion metal plasma” (IMP) sputtering. The second sub-layer 114 is a layer of sputtered titanium which is partially ionized and reacted with nitrogen to form titanium nitride before deposition over first sub-layer 112. The third sub-layer 116 is a layer composed of both sputtered titanium and titanium nitride deposited in a partially ionized state.
To provide the three layer structure of carrier layer 100 as shown in FIG. 1, all three layers 100 are preferably deposited in a single chamber in a continuous process. This may be accomplished, in the case of a titanium based carrier layer, by following the steps of sputtering a titanium target, ionizing at least a portion of the titanium (10% to 100%) before it is deposited on the substrate, attracting the ionized target material to the substrate and forming the first sublayer therewith; then introducing a sufficient quantity of a reactive gas, preferably nitrogen, into the chamber as sputtering and ionization continues and thereby causing all of the material sputtered from the target to react with the gas to form a compound film layer of TiN on the substrate; and then stopping the flow of reactive gas to the chamber while still sputtering the target and ionizing the sputtered target material to form a film layer on the substrate composed of both the base target material, preferably Ti and a reacted product, preferably TiN. Once the Ti/TiN sub-layer has been formed to a sufficient thickness, the power to the system is shut off to stop the sputtering process.
The carrier/barrier layer, once deposited, provides a conformal layer having a thickness of approximately 800 Å, leaving an interior volume 117 within the aperture to be filled with conductive material 119. The conformal carrier/barrier layer 100 was deposited using partially ionized sputtered titanium and titanium nitride, which partially ionized material was directed toward aperture substrates 110 and 111 using an electric field on the substrate support platen (not shown). The equipment used to provide the partially ionized sputtered materials and the electric field on the substrate is described in detail in the Xu et al. patent application, and is described in more general terms below.
The conformal carrier/barrier layer 100 as depicted in the Xu et al. FIG. 1 is achieved only if an adequate electric field (bias) is applied to the support platen (not shown) upon which the substrate sets, thereby imparting a bias to the substrate itself. Typically the substrate bias was about −70V.
We have discovered that application of a substrate bias of about −70 V during the application of layer 112, causes ions to impact on underlying silicon substrate 110 and silicon dioxide sidewall substrate 111, and results in a simultaneous sputtering of these surfaces. Atoms sputtered from silicon substrate 110 and silicon dioxide substrate 111 contaminate surrounding surfaces of other materials as well as the composition of barrier layer 112. The present invention provides a method of depositing and sculpting a sputtered carrier/barrier layer 100 to the desired shape without significantly contaminating or disturbing surrounding surfaces.